1. Field of the Invention
The present invention relates to semiconductor integrated circuits and semiconductor integrated circuit apparatuses including a MOSFET (Metal Oxide Semiconductor Field Effect Transistor; which may be hereafter referred to as a “MOS transistor”) having a large-area.
2. Description of the Related Art
FIG. 29 is a plan view of a structure of a N-channel MOSFET (hereafter referred to as a “NMOS transistor”) having a large-area according to the related art. FIG. 30 is a plan view of a structure of another large-area NMOS transistor according to the related art. FIGS. 29 and 30 are hatched for ease of understanding. The other plan views described below may be also hatched for similar purposes. As illustrated in FIGS. 29 and 30, the large-area NMOS transistors according to the related art include a p-type semiconductor substrate 100 providing a substrate of a conductivity type. Gate electrodes TG11, which may include polysilicon electrodes, are formed on the p-type semiconductor substrate 100. The gate electrodes TG11 are mutually connected by a metal wire W102 via contact electrodes CE. Drain regions D11 and source regions S11 are also formed on the p-type semiconductor substrate 100. The drain regions D11 and source regions S11 include a plurality of n-type active regions AC11 between which the gate electrodes TG11 are disposed. The drain regions D11 and source regions S11 are alternately disposed laterally in FIGS. 29 and 30. A plurality of drain electrodes TD11 are connected to the drain regions D11. The drain electrodes TD11 are mutually connected by a metal wire W104 via through-holes TH. A plurality of source electrodes TS11 are connected to the source regions S11 and are mutually connected by a metal wire W103. The drain regions D11 and the source regions S11 are surrounded by p-type active regions B11 formed on the p-type semiconductor substrate 100. A plurality of substrate electrodes TB11 are connected to the p-type active regions B11. The substrate electrodes TB11 are connected by a metal wire W101. A silicon oxide film 110 is formed between the p-type semiconductor substrate 100, the drain regions D11, the source regions S11, the p-type active regions B11, the gate electrodes TG11, and the metal wires W101 through W104. In the following, the NMOS transistors illustrated in FIGS. 29 and 30 are referred to as a NMOS transistor MN11.
FIG. 31 is a cross section of a structure of the NMOS transistor MN11 according to the related art. The NMOS transistor illustrated in FIG. 31 includes the drain region D11 and the source region S11, which are n-type active regions formed in a p-type well region or the p-type semiconductor substrate 100; the p-type active region B11; a gate oxide film 106 formed on the p-type semiconductor substrate 100; the gate G11 formed on the gate oxide film 106; the drain electrode TD11 connected to the drain region D11; the source electrode TS11 connected to the source region S11; the substrate electrode TB11 connected to the p-type active region B11; and the gate electrode TG11 connected to the gate G11. Between the gate electrode TG11 and the source electrode TS11, a gate-source voltage Vgs is applied. Between the drain electrode TD11 and the source electrode TS11, a drain-source voltage Vds is applied. Between the source region S11 and drain region D11 and the p-type semiconductor substrate 100, a depletion layer region 102 is formed. By applying a gate-source voltage Vgs higher than the potential of the source region S11 by a threshold voltage Vth to the gate electrode TG11, an n-type channel region 101 is formed in a region immediately below the gate G11, whereby the drain region D11 and the source region S11 are electrically connected.
FIG. 32 is a cross section of the NMOS transistor MN11 according to the related art, illustrating impact ionization in the NMOS transistor MN11. As illustrated in FIG. 32, as the drain-source voltage Vds, which is the potential difference between the drain region D11 and the source region S11, is increased, a large electric field is produced between the drain region D11 and the source region S11. As a result, sufficiently accelerated electrons 103 collide with the silicon lattice near the drain region D11, leading to the generation of electron hole pairs 104 in a phenomenon called “impact ionization”. The electrons of the generated electron hole pairs 104 flow via the drain region D11 to the power supply connected to the drain electrode TD11, thus forming part of a drain current. On the other hand, holes 105 of the generated electron hole pairs 104 flow via the depletion layer region 102 to the p-type active region B11, forming a substrate current Isub. The amount of the substrate current Isub depends on the drain-source voltage Vds and the gate-source voltage Vgs of the NMOS transistor MN11.
FIGS. 33 and 34 are graphs illustrating the substrate current Isub with respect to the gate-source voltage Vgs and the drain-source voltage Vds in the NMOS transistor MN11 according to the related art. As illustrated in FIG. 33, the substrate current Isub is increased as the drain-source voltage Vds becomes higher. Further, as illustrated in FIG. 34, the substrate current Isub is greatly increased when the gate-source voltage Vgs is at an intermediate potential such as one half the drain-source voltage Vds.
In order to prevent the generation of the substrate current Isub, it may be effective to reduce the electric field between the drain region D11 and the source region S11 by increasing the gate length of the NMOS transistor, for example. However, this may lead to a decrease in current drive performance of the NMOS transistor.
FIG. 35 is a cross section of a structure of the NMOS transistor MN11 according to the related art, illustrating a circuit diagram of a parasitic bipolar transistor 202 in the NMOS transistor. With reference to FIG. 35, the influence of the flow of the substrate current Isub in the NMOS transistor is described. As illustrated in FIG. 35, the substrate current Isub is observed as a current produced by a current source 201 that flows from the drain electrode TD11 to the substrate electrode TB11. In FIG. 35, a resistance R1 indicates a parasitic resistance of the p-type well region or the p-type semiconductor substrate 100 between the drain electrode TD11 and the substrate electrode TB11. A resistance R2 indicates a parasitic resistance between the substrate electrode TB11 and ground.
When the substrate current Isub is produced, the potential of the p-type well region or the p-type semiconductor substrate 100 is increased by the product of a sum of the resistances R1 and R2 in the path of flow of the substrate current Isub and the substrate current Isub. The npn-type parasitic bipolar transistor 202 includes a collector formed by the drain region D11, which is a n-type active region, a base formed by the p-type active region B11, and a emitter formed by the source region S11, which is an n-type active region. Upon application of a positive base-emitter voltage VBE, the parasitic bipolar transistor 202 conducts when the base-emitter voltage VBE exceeds a threshold voltage.
When the parasitic bipolar transistor 202 conducts, a collector current flows through the parasitic bipolar transistor 202, thereby inducing an increase in the base current and impact ionization. Thus, the drain current of the NMOS transistor and the collector current of the parasitic bipolar transistor 202 are increased at an accelerated rate, resulting in electrical and thermal destruction of the NMOS transistor.
The above phenomenon may also occur in a P channel MOSFET (hereafter referred to as a “PMOS transistor”) having drain regions and source regions which are p-type active regions formed in a n-type well region or a n-type semiconductor substrate, where the relationship of the electrons and holes, the potential relationship, and the polarities of current are reversed from those described above.
FIG. 36 illustrates a cross section and a circuit diagram of an NMOS transistor according to the related art. In the related art illustrated in FIG. 36, the p-type active region B11 is electrically connected to the source region S11, where the operation of the parasitic bipolar transistor 202 is prevented by decreasing the resistances R1 and R2 in the path of flow of the substrate current Isub by various techniques. The techniques may include a “batting source” layout as described in Patent Document 1 by which the source region and the p-type active region are integrally laid out. A method may also be employed by which the p-type active region is connected to the source region by using a low-resistance wire.
However, the NMOS transistor may be used in an application in which a reversal of the potentials of the drain electrode TD11 and the source electrode TS11 may occur such that the potential of the source electrode TS11 may become higher than the potential of the drain electrode TD11. The potential reversal may be caused by a charge/discharge control for a secondary battery or a reverse-flow preventing function. In such an application, a p-n junction 203 between the p-type active region B11 and the drain region D11 illustrated in FIG. 37 is forward-biased when the potential of the source electrode TS11 exceeds the potential of the drain electrode TD11. As a result, an inverse-flow current Irev flows through the p-n junction 203.
In order to prevent the inverse-flow current Irev, the potential of the substrate electrode TB11 may be independently set at a minimum potential at all times. However, in this case, when a positive potential difference develops between the source electrode TS11 and the substrate electrode TB11, the threshold voltage Vth of the NMOS transistor is increased due to a substrate bias effect, resulting in a decrease in the current drive performance of the NMOS transistor.
Thus, in order to prevent the inverse-flow current Irev without lowering the current drive performance of the NMOS transistor, the substrate electrode TB11 and the source electrode TS11 may be electrically connected to or disconnected from each other by a separate NMOS transistor as needed.
FIGS. 38 and 39 each illustrate a cross section and circuit diagram of an NMOS transistor structure according to the related art in which a second NMOS transistor MN12 is provided between the source electrode TS11 and the substrate electrode TB11. A similar circuit is also discussed in Patent Document 2. As illustrated in FIGS. 38 and 39, during a normal operation, a high-level potential is applied to the gate electrode TG12 of the second NMOS transistor MN12 so as to conduct the second NMOS transistor MN12. When the potentials of the source electrode TS11 and the drain electrode TD11 are reversed, the second NMOS transistor MN12 is turned off so as to set the potential of the substrate electrode TB11 at a minimum potential, thus preventing the inverse-flow current Irev.
However, as a result of the provision of the second NMOS transistor MN12 between the substrate electrode TB11 and the source electrode TS11, an on-resistance R2m of the second NMOS transistor MN12 and wiring resistances R2d and R2s in the paths to the second NMOS transistor MN12, which is a separating element, are disposed between the substrate electrode TB11 and the source electrode TS11, as illustrated in FIG. 38. Thus, the resistance of the path through which the substrate current Isub may flow tends to increase. As a result, an operation of the parasitic bipolar transistor 202 is induced.
It is therefore a general object of the present invention to overcome the problems of the related art. A more specific object may be to provide a semiconductor integrated circuit and a semiconductor integrated circuit apparatus having a smaller occupied area than that of the related art and capable of reducing the resistance of the path through which a substrate current flows, and capable of preventing the operation of a parasitic bipolar transistor.    Patent Document 1: Japanese Laid-open Patent Publication No. 2007-273784    Patent Document 2: Japanese Laid-open Patent Publication No. 09-503109